1. Field of the Invention
The present invention relates to an increase in the access speed of a synchronous pseudo SRAM.
2. Description of Related Art
A pseudo SRAM is well known in the art. The pseudo SRAM has the same interface as an SRAM using a memory cell of a DRAM of a related art. That is, the pseudo SRAM includes a refresh control built into a memory, and a controller performs only a read/write control.
Since the pseudo SRAM uses DRAM, which is considered to be unfavorable in terms of speed, for the memory cell and peripheral circuits are integrated, the access speed of the pseudo SRAM is less than SRAM and also genuine DRAM. On the other hand, the pseudo SRAM has advantages of low cost per area and high volume.
Using such advantages, the pseudo SRAMs have often been used in the field of mobile applications that requires cheap and high volume but not high speed accesses.
However in recent years, even in the field that requires high speed accesses, such as network devices, memories are increasing their volumes, so that a DRAM core is required.
Existing SRAMs should be replaced with high volume memories to respond to this demand, however there is an increasing request to speed up the pseudo SRAMs.
There is a limitation in the configuration of the pseudo SRAM that a memory cannot expect when a read/write command will arrive. Therefore, it is necessary to prohibit a refresh operation at the same time as receiving the command, and wait for the refresh to be completed, and then start a read operation.
For example, Japanese Patent No. 3376998 discloses an address access method that operates a semiconductor memory device using a DRAM cell as a general (asynchronous) SRAM.
FIG. 7 is a timing chart according to one exemplary embodiment of Japanese Patent No. 3376998.
The timing chart illustrates an operation of immediately executing a refresh internally in response to a read/write request received from outside, and then performing the read/write request.
In this case, there is a problem that the start of the read operation is delayed by the waiting time for the refresh operation, and thereby slowing down the access. Further, in order to prevent from an internal competition between the refresh and read/write operation, it is necessary to control not to start a new refresh after receiving the read/write command.
Thus, it is desired to remain a pseudo SRAM interface that requires no refresh control and also to increase the speed of accesses.